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XC2S100-5TQG144C Xilinx Features
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• Second generation ASIC replacement technology
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- Densities as high as 5,292 logic cells with up to
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200,000 system gates
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- Streamlined features based on Virtex® FPGA architecture
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- Unlimited reprogrammability
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- Very low cost
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- Cost-effective 0.18 micron process
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• System level features
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- SelectRAM™ hierarchical memory:
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· 16 bits/LUT distributed RAM
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· Configurable 4K bit block RAM
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· Fast interfaces to external RAM
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- Fully PCI compliant
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- Low-power segmented routing architecture
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- Full readback ability for verification/observability
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- Dedicated carry logic for high-speed arithmetic
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- Efficient multiplier support
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- Cascade chain for wide-input functions
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- Abundant registers/latches with enable, set, reset
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- Four dedicated DLLs for advanced clock control
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- Four primary low-skew global clock distribution
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nets
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- IEEE 1149.1 compatible boundary scan logic
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• Versatile I/O and packaging
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- Pb-free package options
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- Low-cost packages available in all densities
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- Family footprint compatibility in common packages
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- 16 high-performance interface standards
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- Hot swap Compact PCI friendly
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- Zero hold time simplifies system timing
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• Core logic powered at 2.5V and I/Os powered at 1.5V,
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2.5V, or 3.3V
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• Fully supported by powerful Xilinx® ISE® development
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system
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- Fully automatic mapping, placement, and routing
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XC2S100-5TQG144C Xilinx Datasheet: |